1. Field of the Invention
The invention relates to a slicing device, more particularly to a digital slicing device for application to a communications system.
2. Description of the Related Art
In a communications system, a transmitting end performs channel encoding upon information to be transmitted prior to transmission in order to reduce a bit error rate. As shown in FIG. 1, a transmitting end 100 first converts 7-bit information (u1-u3, c1-c4) into two 4-bit signals (x1) (x2) through a DSQ128 converting unit 10, subsequently modulates the 4-bit signals (x1), (x2) into modulated symbols (a1), (a2) having one of sixteen levels {±1, ±3, ±5, . . . , ±15} through a modulating unit 11, and finally converts the modulated symbols (a1), (a2) to analog 16-PAM symbols for subsequent transmission.
Accordingly, as shown in FIG. 2, when a receiving end 200 receives a signal, the signal is first suitably amplified by an automatic gain controller 201, then filtered by a lowpass filter 202 to remove high frequency noise components, and subsequently sent to an analog-to-digital (A/D) converter 203 for conversion into a digital signal (which is essentially the modulated symbols in the transmitting end 100). After suppressing near end crosstalk (NEXT), echo, and far end crosstalk (FEXT) through a NEXT suppressor 204, an echo suppressor 205, and a FEXT suppressor 206, respectively, the digital signal is then fed to a feed forward equalizer 207 to eliminate the effect of a previous modulated symbol, suitably amplified by a digital automatic gain controller 208, and subsequently sent to a channel decoder 209 for channel decoding, thereby extracting the 7-bit information (u1-u3, c1-c4) from the modulated symbols sent by the transmitting end 100.
In the meantime, the receiving end 200 uses a slicer 211 and an error term generator 212 to generate an error term in real-time according to the output of the digital automatic gain controller 208. The error term is provided to various components, such as the NEXT suppressor 204, the echo suppressor 205, the FEXT suppressor 206, the feed forward equalizer 207, the digital automatic gain controller 208, a timing recovery circuit 210 that is responsible for correcting timing of the A/D converter 203, etc., for real-time update.
The slicer 211 makes a numerical value determination with respect to each inputted modulated symbol in sequence according to the modulation levels, e.g., {±1, 3, ±5, . . . , ±15}, employed by the modulating unit 11 of the transmitting end 100. If the slicer 211 receives a modulated symbol (1.5), the slicer 211 determines from the modulation levels {±1, ±3, ±5, . . . , ±15} that the modulated symbol (1.5) is closer to the level (1), and outputs the symbol (1) as a determination result. At this time, the error term generator 212 coupled between input and output ends of the slicer 211 calculates an error term to be (0.5) based on the input and output signals of the slicer 211.
However, when the modulated signal is subjected to severe noise interference during transmission such that an original level (1) becomes (2.5), the slicer 211 will erroneously output the symbol (3) as its determination result, and the error term generator 212 erroneously generates an error term (−0.5) (the result of 2.5-3, while the correct error term should be 2.5−1=1.5). Updating using the incorrect error term leads to improper operations of the NEXT suppressor 204, the echo suppressor 205, the FEXT suppressor 206, the feed forward equalizer 207, the digital automatic gain controller 208, and the timing recovery circuit 210, thereby adversely affecting decoding efficiency of the channel decoder 209 and hindering reduction of the bit error rate.